The need for lightweight, thin, low cost packaging materials for integrated circuit (IC) applications such as consumer products has led to development and use of a method of connecting IC chips termed tape automated bonding (TAB). TAB involves forming electrical leads for IC chips on thin, flexible tape which is similar in appearance to 35 mm film. The tape is electrically insulative, and the leads are typically formed from a thin layer of metal which has been deposited on the tape and photolithographically etched. The precisely formed leads are aligned with and bonded to signal terminals from the integrated circuit located near a perimeter of a surface of the chip. The signal terminals of the chip are often termed "bond pads." The leads extend outwardly from the chip for connection with an external element, often called a "package" or "assembly."
A problem with TAB is that the leads may be only a few thousandths of an inch in cross-section and are cantilevered from the tape at the point where the leads are to be bonded to the terminals of the chip. These tiny, cantilevered electrical leads are thus the only mechanical support between the chip and the package at the edge of the chip, an area prone to deformational stress from any change in position of the chip relative to the package. As a result, the leads may break at this point, causing the chip and package to fail.
Another problem with TAB is that the leads fan outwardly from the chip for bonding to the package, and thus require a larger package area than that dictated by the size of the chip. It is often desirable, and appears to be a long term trend in electronics, to condense information capabilities in smaller packages, and the larger area or "footprint" required by traditional TAB packaging stands in the way of this trend.
Another type of electrical and mechanical connection of an IC chip to a package is called "flip-chip" or "controlled collapse chip connection" (C4), and is described in U.S. Pat. Nos. 3,401,126 and 3,429,040 to Lewis. C4 involves forming solder balls on the surface of the chip that connect signal terminals of the chip with corresponding connections on the package, the solder balls providing both electrical contacts and mechanical support between the chip and the package.
One difficulty with the flip chip type interconnection is that the thermal coefficient of expansion is usually significantly different for the chip, often formed of silicon, and the package, typically made of ceramic and materials conventionally used in forming printed circuit boards. As a result, changes in temperature of the chip or substrate, or both, lead to stresses between the solder balls and the chip or substrate. This may cause the solder ball connections to break, or may cause stresses within the chip that create chip failures.
Another difficulty with the flip-chip interconnections is that they do not allow testing prior to committing the chip to the package, other than wafer probe testing which does not allow testing with all the signal terminals connected or "burn-in" testing such as can be performed with TAB. This difficulty is underscored by the realization that it is often more appropriate to speak of committing the package to the chip rather than the chip to the package, since discarding even a multi-chip package may be more economical than trying to determine which chip of the module failed and to then replace that chip.
Yet another difficulty with this technology is that many IC chips are designed and built with bond pads formed in a row near the perimeter of the chip surface. Since a chip may have well over 500 such bond pads, the organizing of these terminals into a row requires that the terminals and the separation between the terminals be too small to reliably form effective solder bumps for connection to a package.
One approach to overcoming these difficulties is described in U.S. Pat. No. 4,472,876 to Nelson, which teaches a flexible area bonding tape containing electrical paths connecting a chip to a package. The tape and conductive paths absorb stresses caused by thermal expansion and also conduct heat from the chip to the package, thereby reducing expansion stress. The approach of Nelson, however, requires an interconnection package having a larger footprint than that of the chip. Another approach is described in U.S. Pat. Nos. 5,148,265 and 5,148,266, both issued to Khandros et al., which also describe an insulative tape having conductive leads connecting terminals on a chip with those on a substrate. The interconnection with the substrate does not fan out, instead being located in an array having an area equal to or less than that of the chip surface, but the chip is tested with wafer probes. This wafer probe testing does not allow testing of all the functions of a chip, is more expensive than TAB testing, and has additional disadvantages caused by a reduction of thermal conductivity created to accommodate the wafer probe testing.
It is an object of the present invention to provide improved testing of a chip prior to interconnection to a package, while that interconnection occupies a surface no larger than that of the chip.